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19-0874; Rev 0; 7/07
High-Voltage OVP with Battery Switchover
General Description
The MAX4959/MAX4960 overvoltage protection controllers protect low-voltage systems against high-voltage faults of up to +28V. When the input voltage exceeds the overvoltage lockout (OVLO) threshold, these devices turn off an external pFET to prevent damage to the protected components. The undervoltage lockout (UVLO) threshold holds the external pFET off until the input voltage rises to the correct level. An additional safety feature latches off the pFET when an incorrect low-power adapter is plugged in. The MAX4959/MAX4960 control an external battery switchover pFET (P2) (see Figures 4 and 6) that switches in the battery when the AC adapter is unplugged. The undervoltage and overvoltage trip levels can be adjusted with external resistors. The input is protected against 15kV HBM ESD when bypassed with a 1F ceramic capacitor to ground. All devices are available in a small 10-pin (2mm x 2mm) DFN and 10-pin MAX packages and are specified for operation over the extended -40C to +85C temperature range. o Overvoltage Protection Up to +28V o 2.5% Accurate Externally Adjustable OVLO/UVLO Thresholds o Battery Switchover pFET Control o Protection Against Incorrect Power Adapter o Low (100A Typ) Supply Current o 25ms Input Debounce Timer o 25ms Blanking Time o 10-Pin (2mm x 2mm) DFN and 10-Pin MAX Packages
Features
MAX4959/MAX4960
Ordering Information
PART TEMP RANGE PINTOP PACKAGE MARK 10 DFN 10 MAX 10 DFN 10 MAX AAO -- AAP -- PKG CODE L1022-1 U10-1 L1022-1 U10-1
MAX4959ELB+ -40C to +85C MAX4959EUB+* -40C to +85C MAX4960ELB+ -40C to +85C MAX4960EUB+* -40C to +85C
Applications
Notebooks Laptops Camcorders Ultra-Mobile PCs
+Denotes a lead-free package. *Future product--Contact factory for availability.
Pin Configurations
GND
N.C.
VDD
CB
TOP VIEW
GATE2
+
10
9
8
7
6
GATE1 N.C. (SOURCE1)
1 2 3 4 5
6 7
GATE2 N.C. GND CB VDD
MAX4959 MAX4960 +
1 GATE1 2 N.C. (SOURCE1) 3 IN 4 UVS 5 OVS
IN UVS OVS
MAX4959 MAX4960
8 9 10
MAX
DFN
( ) MAX4960 ONLY.
Typical Operating Circuits appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing delivery, and ordering information please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
High-Voltage OVP with Battery Switchover MAX4959/MAX4960
ABSOLUTE MAXIMUM RATINGS
IN, SOURCE1, GATE1, GATE2, to GND ................-0.3V to +30V VDD to GND ..............................................................-0.3V to +6V UVS, OVS, CB to GND .............................................-0.3V to +6V Continuous Power Dissipation (TA = +70C) 10-pin DFN (derate 5.0mW/C above +70C) ...........403mW 10-pin MAX (derate 5.6mW/C above +70C) ...........444mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = +19V, TA = -40C to +85C, unless otherwise noted, CVDD = 100nF. Typical values are at TA = +25C.) (Note 1)
PARAMETER IN Input Voltage Range Overvoltage Adjustable Trip Range Overvoltage Comp Reference OVS Input Leakage Current Overvoltage Trip Hysteresis Undervoltage Adjustable Trip Range Undervoltage Comp Reference UVS Input Leakage Current Undervoltage Trip Hysteresis Internal Undervoltage Trip Level Internal Undervoltage Trip Hysteresis Power-On Trip Level Power-On Trip Hysteresis IN Supply Current VDD VDD Voltage Range VDD Undervoltage Lockout VDD Undervoltage Lockout Hysteresis VDD Supply Current GATE_ GATE1 Open-Drain MOS RON Resistance GATE2 Open-Drain MOS RON Resistance RON RON VCB = 0V, VIN = 19V, VOVS < OVREF and VUVS > UVREF, IGATE_ = 0.5mA (MAX4959) VCB = 3V, IGATE_ = 0.5mA 1 1 k k VDD VDDUVLO VDDUVLOHYS IVDD VDD = +5V, VIN = 0V VDD falling edge 2.7 1.55 50 10 5.5 2.40 V V mV A VIN OVLO OVREF OVILKG OVHYS UVLO UVREF UVILKG UVHYS INTUVREF INTUVHYS POTL POTLHYS IIN VIN = +19V, VOVS < OVREF and VUVS > UVREF VDD > +3V, IN rising edge 0.5 VIN falling edge 4.1 (Note 2) VIN falling edge 5 1.18 -100 1 4.4 1 0.75 10 100 300 1 4.7 1.228 (Note 2) VIN rising edge 4 6 1.18 -100 1 28 1.276 +100 1.228 28 28 1.276 +100 V V V nA % V V nA % V % V % A SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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High-Voltage OVP with Battery Switchover
ELECTRICAL CHARACTERISTICS (continued)
(VIN = +19V, TA = -40C to +85C, unless otherwise noted, CVDD = 100nF. Typical values are at TA = +25C.) (Note 1)
PARAMETER GATE1 Leakage Current GATE2 Leakage Current CB Logic-Level High Logic-Level Low CB Pulldown Resistor TIMING Debounce Time GATE1 Assertion Delay from CB Pin GATE2 Assertion Delay from CB Pin Blanking Time MAX4960 SOURCE1/GATE1 Resistance GATE1/Ground Resistance RSG RGG (MAX4960) GATE1 Asserted (MAX4960) 140 140 200 200 260 260 k k tDEB t1GATE t2GATE tBLANK VOVP > VIN > VUVP for greater than tDEB for GATE1 to go low CB = +3V to 0 rise time = fall time = 5ns (Note 3) CB = 0 to +3V rise time = fall time = 5ns (Note 3) 10 10 25 50 50 25 40 40 ms ns ns ms VIH VIL RCBPD 1 2 1.5 0.4 3 V V M SYMBOL G1ILKG G2ILKG VCB = 0V CONDITIONS VOVS > OVREF, VUVS < UVREF, or VCB = +5V MIN -1 -1 TYP MAX +1 +1 UNITS A A
MAX4959/MAX4960
Note 1: Operation is tested at TA= +25C and guaranteed by design for DFN package. Operation over specified temperature range is tested for MAX package. Note 2: Do not exceed absolute maximum rating; the ratio between the externally set OVLO and UVLO threshold must not exceed 4, [OVLO/UVLO]MAX 4. Note 3: Assertion delay starts from switching of CB pin to reaching of 80% of GATE1/GATE2 transition. This delay is measured without external capacitive load.
Typical Operating Characteristics
(VOVLO = 22.2V and VUVLO = 10.1V, R1 = 887k, R2 = 66.5k, R3 = 54.9k, all resistors 1%, OVREF = UVREF = 1.228V.)
UNDERVOLTAGE RESPONSE (WITHIN BLANKING TIME) (RPULLUP = 1k)
MAX4959/60 toc02
POWER-UP RESPONSE (RPULLUP = 1k)
MAX4959/60 toc01
OVERVOLTAGE RESPONSE (RPULLUP = 5k)
30 VIN 25 20 15 10 5 0 VGATE1 VDD 16 14 12 VOLTAGE (V) 10 8 6 4 2 0 -150 -100 -50 0 50 TIME (s) 100 150 0 VIN
10 8 VOLTAGE (V) 6 4 2 0 -2 -150 -100
VIN VGATE1
DRAIN OF P1
VDD
VOLTAGE (V)
VGATE1
-50
0 TIME (s)
50
100
150
10
20
30
40
50
60
70
TIME (s)
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MAX4959/60 toc03
12
3
High-Voltage OVP with Battery Switchover MAX4959/MAX4960
Typical Operating Characteristics (continued)
(VOVLO = 22.2V and VUVLO = 10.1V, R1 = 887k, R2 = 66.5k, R3 = 54.9k, all resistors 1%, OVREF = UVREF = 1.228V.)
BATTERY SWITCHOVER WITH ADAPTERPLUGGED RESPONSE (VIN = 19V, VGATE2-PULLUP = 4.2V, RPULLUP = 5k)
MAX4959/60 toc05
LOW-POWER ADAPTER RESPONSE (VOVLO = 22.3V, VUVLO = 10.1V, pFET = IRF7726)
MAX4959/60 toc04
OVERVOLTAGE AND UNDERVOLTAGE TRIP DIFFERENCE vs. TEMPERATURE (RPULLUP = 1k)
4 3 2 VOLTAGE (V) UV TRIP DIFF
MAX4959/60 toc06
13 11 9 VOLTAGE (V)
25 20 15 10 5 VGATE1 VGATE2 CB
5
VOLTAGE (V)
VIN 7 5 3 1 -1 0 .05 0.1 0.15 LOAD BECOMES PRESENT
VGATE1
1 0 -1 -2 -3 -4 OV TRIP DIFF
DRAIN OF P1
0 -5
0.2 0.25 0.3 TIME (s)
-5 -150 -100 -50 0 50 TIME (s) 100 150 -50 -30 -10 10 30 50 70 90 TEMPERATURE (C)
SUPPLY CURRENT vs. INPUT VOLTAGE
MAX4959/60 toc07
LOGIC-INPUT THRESHOLD vs. TEMPERATURE
1.8 1.6 LOGIC THRESHOLD (V) 1.4 1.2 1 0.8 0.6 0.4 0.2 0 3.5 -50 -30 -10 10 30 50 70 90 VTH-LO VTH-HI
MAX4959/60 toc08
VDD SUPPLY CURRENT vs. TEMPERATURE
MAX4959/60 toc09
2
5
200 160 ISUPP (A) 120 80 40 0 -40 0 5 10 15 VIN (V) 20 25
VDD SUPPLY CURRENT (A)
4.5
4
-50
-30
-10
10
30
50
70
90
110
TEMPERATURE (C)
TEMPERATURE (C)
VOLTAGE RANGE vs. INPUT VOLTAGE RANGE
MAX4959/60 toc10
6 5 4 VDD (V) 3 2 1 0 0 5 10 15 VIN (V) 20 25
4
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High-Voltage OVP with Battery Switchover
Pin Description
PIN MAX4959 1 2, 9 -- 3 MAX4960 1 9 2 3 NAME FUNCTION pFET Gate Drive Output Open Drain. GATE1 is actively driven low, except during fault (OVP or UVP) condition (the external PFET is turned off). When VUVLO < VIN < VOVLO, GATE1 is driven low (the external PFETP1 is turned on). No Connection. Not internally connected. (Connect to ground or leave unconnected.) pFET Source Output. An internal resistor is connected between SOURCE1 and GATE1. Voltage Input. IN is both the power-supply input and the overvoltage/undervoltage sense input. Bypass IN to GND with a 1F ceramic capacitor to get a 15kV protected input. A minimum 0.1F ceramic capacitor is required for proper operation. Undervoltage Threshold Set Input. Connect UVS to an external resistive divider from IN to GND to set the undervoltage lockout threshold. (See Typical Operating Circuits.) Overvoltage Threshold Set Input. Connect OVS to an external resistive divider from IN to GND to set the overvoltage lockout threshold. (See Typical Operating Circuits.) Internal Power-Supply Output. Bypass VDD to GND with a 0.1F minimum capacitor. VDD powers the internal power-on reset circuits. (See the VDD Capacitor Selection section.) Battery Switchover Control Input. When CB is high, GATE1 is high (P1 is off), and GATE2 is low (P2 is on). When CB is low, GATE1 is controlled by internal logic and GATE2 is high (P2 is off). GATE1 is controlled by CB only if VULO < VIN < VOVLO. Ground pFET Gate Drive Output, Open Drain. When CB is high, GATE2 is low (P2 is on). When CB is low, GATE2 is high impedance (P2 is off).
MAX4959/MAX4960
GATE1 N.C. SOURCE1 IN
4 5 6
4 5 6
UVS OVS VDD
7 8 10
7 8 10
CB GND GATE2
Detailed Description
The MAX4959/MAX4960 provide up to +28V overvoltage protection for low-voltage systems. When the input voltage exceeds the overvoltage trip level, the MAX4959/ MAX4960 turn off an external pFET to prevent damage to the protected components. The MAX4959/MAX4960 feature a control bit (CB) pin that controls an external battery-switchover function that switches in the battery when the adapter is unconnected. The host system detects when the battery switchover must take place and pulls CB high to turn on P2. The load current is not interrupted during battery switchover as the body diode of P2 conducts until the CB line is driven high (see the MAX4959 Typical Operating Circuit 1, Figure 4). An additional safety feature latches off pFET P1 when a low-power adapter is plugged in. This protects the system from seeing repeated adapter insertions and removals when an incorrect low-power adapter is plugged in that cannot provide sufficient current.
Undervoltage Lockout (UVLO)
The MAX4959/MAX4960 have an adjustable undervoltage lockout threshold ranging from +5V to +28V. When VIN is less than the VUVLO, the device waits for a blanking time, tBLANK, to see if the fault still exists. If the fault does not exist at the end of tBLANK, P1 remains on. If VIN is less than VUVLO for longer than the blanking time, the device turns P1 off and P1 does not turn on again until VIN < 0.75V. See Figure 1.
Overvoltage Lockout (OVLO)
The MAX4959/MAX4960 have an adjustable overvoltage lockout threshold ranging from +6V to +28V. When VIN is greater than the VOVLO, the device turns P1 off immediately. When VIN drops below VOVLO, P1 turns on again after the debounce time has elapsed.
Device Operation
High-Voltage Adapter (VIN > VOVLO) If an adapter with a voltage higher than V OVLO is plugged in, the MAX4959/MAX4960 is in an OVP condition, so P1 is kept off or immediately turned off. There is
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5
High-Voltage OVP with Battery Switchover MAX4959/MAX4960
Functional Diagrams
Functional Diagram for the MAX4959
IN GATE1 GATE2
+ N VDD -
VSG
N1 BANDGAP
N2
ANALOG SUPPLY CB
DIGITAL SUPPLY
+ VREF2 = 0.7V + VREF1 = 2V
POWER ON POWER-ON RESET AND OFF STORAGE LOGIC
VDD UVLO
GND + UVLOINT + + UVLO
OVS
OVLO
UVS
MAX4959
-
no blanking time for OVP, but the debounce time applies once the IN voltage falls below V OVLO but above VUVLO. When the voltage at IN is higher than VOVLO, the CB pin does not control P1.
Correct Adapter (VUVLO < VIN < VOVLO) In this case, when the adapter is plugged in, the device goes through a 20ms (typ) debounce time and ensures that the voltage at IN is between VUVLO and VOVLO before P1 is turned on. In this state, the CB pin controls both P1 and P2.
Low-Power Adapter or Glitch Condition If the adapter has the correct voltage but not enough power (incorrect low-power adapter), the MAX4959/ MAX4960 protect pFET P1 from oscillation. When the adapter is first plugged in, P1 is off so the voltage is correct. When P1 is turned on after the debounce time, the low-power adapter is dragged down to below VUVLO. The device waits for a 10ms blanking time to make sure it is not a temporary glitch, and, if a fault still exists, it latches off P1. P1 does not turn on again until the adapter is unplugged (VIN<~0.75V) and plugged in again. This feature can work without the battery present
6
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High-Voltage OVP with Battery Switchover
Functional Diagrams (continued)
Functional Diagram for the MAX4960
MAX4959/MAX4960
IN
SOURCE1
GATE1
GATE2
+ N VDD -
VSG
N2 BANDGAP N1 ANALOG SUPPLY CB
DIGITAL SUPPLY
+ VREF2 = 0.7V + VREF1 = 2V
POWER ON POWER-ON RESET AND OFF STORAGE LOGIC
VDD UVLO
GND + UVLOINT + + UVLO
OVS
OVLO
UVS
MAX4960
-
only if the backup capacitor on VDD is large enough to maintain power for greater than the 10ms blanking time. The detection that the adapter is unplugged and plugged in again is implemented by monitoring the VIN signal. The adapter is unplugged when VIN drops below VIN =~ 0.75V, and it is plugged in when VIN becomes greater than VIN =~ 0.75V. To ensure the monitoring of this lower threshold, an external storage capacitor at the VDD pin is necessary. When the input voltage VIN drops below 4V, power for some internal VIN monitoring circuitry is supplied by the external capacitor at the VDD pin.
This capacitor is supplied by VIN through a diode and is internally limited to 5.5V.
Adapter Not Present (VIN < VUVLO) When the input voltage VIN drops below 4.4V, P1 is turned off automatically and P1 does not turn on again until the adapter is unplugged (V IN <~0.75V) and plugged in again. When the adapter is not present, P1 is kept off with the gate-source resistor (which is internal for the MAX4960 and external for the MAX4959), and the CB pin controls the battery switchover pFET P2.
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7
High-Voltage OVP with Battery Switchover MAX4959/MAX4960
VIN VOVLO VOVLO VUVLO INTUVREF VUVLO
tDEB VGATE1
tDEB
tBLANK
tDEB
tBLANK
VDD
VDD REGULATED
VCB
VGATE2
Figure 1. Timing Diagram
The following table lists the different modes of operations:
IN RANGE VIN > VOVLO VUVLO < VIN < VOVLO (debounce timeout ongoing) VUVLO < VIN < VOVLO (debounce timeout elapsed) VINTUVREF < VIN < VOVLO (blanking timeout ongoing) VINTUVREF < VIN < VOVLO (blanking timeout elapsed) VIN < VINTUVREF P1 STATE P1 OFF (not affected by CB) P1 OFF (not affected by CB) CB = 1 -> P1 is OFF CB = 0 -> P1 is ON CB = 1 -> P1 is OFF CB = 0 -> P1 is ON P1 OFF (not affected by CB). P1 does not turn on again until adapter is unplugged (VIN <~0.75V) and plugged in again. P1 OFF (not affected by CB). P1 does not turn on again until adapter is unplugged (VIN <~0.75V) and plugged in again. CB = 1 -> P2 is ON CB = 0 -> P2 is OFF P2 STATE
8
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High-Voltage OVP with Battery Switchover
Applications Information
MOSFET Configuration and Selection
The MAX4959/MAX4960 are used with a single MOSFET configuration as shown in the Typical Operating Circuits to regulate voltage as a low-cost solution. The MAX4959/MAX4960 are designed with pFETs. For lower on-resistance, the external MOSFET can be multiple pFETs in parallel. In most situations, MOSFETs with RDS(ON) specified for a VGS of 4.5V work well. Also, MOSFETs (with VDS 30V) withstand the full +28V IN range of the MAX4959/MAX4960. Note that the ratio between the externally set OVLO and UVLO threshold must not exceed: 4 [VOVLO / VUVLO]MAX 4)
MAX4959/MAX4960
VDD Capacitor Selection VDD is regulated to +5V by a linear regulator. Since the minimum external adjustable UVLO trip threshold is +5V, the VDD range is +5V to +28V and the value at VDD is: VDD = VIN - 0.8V where VIN = 5V to 5.8V
VDD = +5V where VIN > 5.8V The capacitor at VDD must be large enough to provide power to the device for an external settable time, tHOLD, when VIN drops to 0V. The capacitor value to have a minimum time of tHOLD is: C = (IVDD x tHOLD) / (VDD - VDDUVLO) The worst case scenario is where VIN = +5V, VDD = VIN - 0.8V = +4.2V, IVDD = 10A (max). For a tHOLD time of 20ms, C = (10A x 20ms) / (4.2V - 2.2V) = 100nF. Note: The capacitor must be greater than 100nF for the internal regulator to be stable, and needs to have low ESR and low leakage current, for example, a ceramic capacitor.
Resistor Selection for Overvoltage/Undervoltage Window
The MAX4959/MAX4960 include undervoltage and overvoltage comparators for window detection (see Figure 4). GATE1 is enhanced and after the debounce time, the pFET is turned on when the monitored voltage is within the selected window. The resistor values R1, R2, and R3 can be calculated as follows: R VUVLO = (UVREF ) TOTAL R2 + R 3 R VOVLO = (OVREF ) TOTAL R3 where RTOTAL = R1 + R2 + R3. Use the following steps to determine the values for R1, R2, and R3: 1) Choose a value for RTOTAL, the sum of R1, R2, and R3. Because the MAX4959/4960 have very high input impedance, RTOTAL can be up to 5M. 2) Calculate R3 based on R TOTAL and the desired VOVLO trip point: OVREF x R TOTAL R3 = VOVLO 3) Calculate R2 based on RTOTAL, R3, and the desired VUVLO trip point: UV x R TOTAL R2 = REF - R3 VUVLO 4) Calculate R1 based on RTOTAL, R2, and R3: R1 = RTOTAL - R2 - R3
IN Bypass Considerations
For most applications, bypass IN to GND with a 1F ceramic capacitor. If the power source has significant inductance due to long lead length, take care to prevent overshoots due to the LC tank circuit, and provide protection if necessary to prevent exceeding the +30V absolute maximum rating on VIN. The MAX4959/MAX4960 provide protection against voltage faults up to+28V, but this does not include negative voltages. If negative voltages are a concern, connect a Schottky diode from IN to GND to clamp negative input voltages.
ESD Test Conditions
The MAX4959/MAX4960 are protected from 15kV Human Body Model ESD on IN when IN is bypassed to ground with a 1F ceramic capacitor.
Human Body Model
Figure 2 shows the Human Body Model and Figure 3 shows the current waveform it generates when discharged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest that is then discharged into the device through a 1.5k resistor.
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9
High-Voltage OVP with Battery Switchover MAX4959/MAX4960
RC 1M CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE RD 1.5k DISCHARGE RESISTANCE DEVICE UNDER TEST IP 100% 90% AMPERES Cs 100pF STORAGE CAPACITOR 36.8% 10% 0 0 tRL TIME tDL CURRENT WAVEFORM Ir PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE)
Figure 2. Human Body ESD Test Model
Figure 3. Human Body Current Waveform
Chip Information
PROCESS: BiCMOS
10
______________________________________________________________________________________
High-Voltage OVP with Battery Switchover
Typical Operating Circuits
MAX4959/MAX4960
D1 AC ADAPTER P1 C1 RU1 C2 RD1 IN VSUPPLY GATE2 N2 P2 GATE1 RU2 RD2 BATTERY CHARGER DC-DC CONVERTER
VDD
HOLD-UP POWER SUPPLY
N1
CB
R1 UVS
VREF
UVLO R2 OVS OVLO R3 LOGIC
GND
1-CELL (4.2V) TO 4-CELL (16.8V)
Figure 4. MAX4959 Typical Operating Circuit 1
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11
High-Voltage OVP with Battery Switchover MAX4959/MAX4960
Typical Operating Circuits (continued)
AC ADAPTER
28V PROTECTED CHARGER EN 3.3V RD1
DC-DC CONVERTER
IN VSUPPLY
GATE1 SYSTEM LOAD GATE2 N2
VDD
HOLD-UP POWER SUPPLY
N1
CB
R1 UVS
VREF
UVLO R2 OVS OVLO R3 LOGIC
GND
1-CELL (4.2V) TO 4-CELL (16.8V)
Figure 5. MAX4959 Typical Operating Circuit 2
12
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High-Voltage OVP with Battery Switchover
Typical Operating Circuits (continued)
MAX4959/MAX4960
AC ADAPTER P1 C1 C2
DC-DC CONVERTER
IN VSUPPLY
SOURCE1
GATE1
RU2 RD2 BATTERY CHARGER GATE2 N2 P2
VDD
HOLD-UP POWER SUPPLY
N1
CB
R1 UVS
VREF
UVLO R2 OVS OVLO R3 LOGIC
GND
1-CELL (4.2V) TO 4-CELL (16.8V)
Figure 6. MAX4960 Typical Operating Circuit 1
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13
High-Voltage OVP with Battery Switchover MAX4959/MAX4960
Typical Operating Circuits (continued)
AC ADAPTER P1 C1
BATTERY CHARGER
DC-DC CONVERTER
IN VSUPPLY
SOURCE1
GATE1 SYSTEM LOAD GATE2 N2
VDD
HOLD-UP POWER SUPPLY
N1
CB
R1 UVS
VREF
UVLO R2 OVS OVLO R3 LOGIC
GND
1-CELL (4.2V) TO 4-CELL (16.8V)
Figure 7. MAX4960 Typical Operating Circuit 2
14
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High-Voltage OVP with Battery Switchover
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 6, 8, 10L UDFN.EPS
MAX4959/MAX4960
D
A
e
b
N
XXXX XXXX XXXX
SOLDER MASK COVERAGE
E
PIN 1 0.10x45
L L1
PIN 1 INDEX AREA SAMPLE MARKING 7 1 A A
(N/2 -1) x e)
C L
C L
b A A2 A1
L e
EVEN TERMINAL
L e
ODD TERMINAL
PACKAGE OUTLINE, 6, 8, 10L uDFN, 2x2x0.80 mm
-DRAWING NOT TO SCALE-
21-0164
A
1 2
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15
High-Voltage OVP with Battery Switchover MAX4959/MAX4960
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS SYMBOL A A1 A2 D E L L1 MIN. 0.70 0.15 0.020 1.95 1.95 0.30 NOM. 0.75 0.20 0.025 2.00 2.00 0.40 0.10 REF. MAX. 0.80 0.25 0.035 2.05 2.05 0.50
PACKAGE VARIATIONS PKG. CODE L622-1 L822-1 L1022-1 N 6 8 10 e 0.65 BSC 0.50 BSC 0.40 BSC b 0.300.05 0.250.05 0.200.03 (N/2 -1) x e 1.30 REF. 1.50 REF. 1.60 REF.
PACKAGE OUTLINE, 6, 8, 10L uDFN, 2x2x0.80 mm
-DRAWING NOT TO SCALE-
21-0164
A
2 2
16
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High-Voltage OVP with Battery Switchover
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
10LUMAX.EPS
MAX4959/MAX4960
e
10
4X S
10
INCHES MAX DIM MIN 0.043 A 0.006 A1 0.002 A2 0.030 0.037 0.120 D1 0.116 0.118 D2 0.114 E1 0.116 0.120 0.118 E2 0.114 0.199 H 0.187 L 0.0157 0.0275 L1 0.037 REF b 0.007 0.0106 e 0.0197 BSC c 0.0035 0.0078 0.0196 REF S 0 6
MILLIMETERS MAX MIN 1.10 0.05 0.15 0.75 0.95 2.95 3.05 2.89 3.00 2.95 3.05 2.89 3.00 4.75 5.05 0.40 0.70 0.940 REF 0.177 0.270 0.500 BSC 0.090 0.200 0.498 REF 0 6
H
O0.500.1
0.60.1
1
1
0.60.1
TOP VIEW
BOTTOM VIEW
D2 GAGE PLANE A2 A b A1 D1
E2
c
E1 L1
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 10L uMAX/uSOP
APPROVAL DOCUMENT CONTROL NO. REV.
21-0061
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Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17
(c) 2007 Maxim Integrated Products
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is a registered trademark of Maxim Integrated Products, Inc.

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Price & Availability of MAX4960EUB

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